1. Field of the Invention
The invention relates to single-ended signal sensing circuitry and more particularly to sense amplifiers for sensing single-ended memory cell readouts and providing corresponding digital output signals.
2. Background Art
A present state of the art read-only memories (ROMs) consists of a large number of individual memory cells representing a plurality of multi-bit words. The presence or absence of a gate in the memory cell determines whether the digital 1 or digital 0 state, respectively, is stored. When a particular cell is read, a small voltage signal corresponding to the state of the cell is generated on a bit line connected to a sense amplifier. The sense amplifier discriminates between the absence of gate, representative of a digital 0 state, and the presence of a gate, representative of a digital 1 state, and amplifies the received signal. High performance, high density ROMs are preferably read at a very high speed to be compatible with the very high speed microprocessors. One of the greatest impediments to high speed performance is in the circuitry for sensing and amplifying an analog array cell signal on a single bit line into a full swing digital signal. One of the major problems in rapid readout of an analog signal is the time required to discriminate between a 0 signal and a 1 signal, and the time required produce an output signal once the input signal has been properly discriminated.
Certain prior art ROM sense amplifier designs require a large bit line voltage swing to properly trigger the state of the signal detection circuitry, thus increasing the memory access time. Other prior art sense amplifier designs require two columns of "dummy" reference cells to generate an internal voltage reference to a differential sense amplifier, resulting in increased design complexity area and power. When a binary signal is read from a high speed sensory, the time required for signal transition from one binary state to the other is a significant portion of the read-out window. As a result a significant period of time is required in a sense amplifier to generate a full value binary output signal, adding a substantial delay in sensing a signal.